diff -uprN -X linux-source-2.6.32.orig/Documentation/dontdiff linux-source-2.6.32.orig/drivers/char/agp/intel-agp-add.h linux-source-2.6.32.patched/drivers/char/agp/intel-agp-add.h --- linux-source-2.6.32.orig/drivers/char/agp/intel-agp-add.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-source-2.6.32.patched/drivers/char/agp/intel-agp-add.h 2010-04-29 00:35:01.463625893 +0200 @@ -0,0 +1,10 @@ +void wbinvd_on_cpu(int cpu); +static int wbinvd_on_all_cpus(void); + +#define wbinvd_on_cpu(cpu) wbinvd() +static inline int wbinvd_on_all_cpus(void) +{ + wbinvd(); + return 0; +} + diff -uprN -X linux-source-2.6.32.orig/Documentation/dontdiff linux-source-2.6.32.orig/drivers/char/agp/intel-agp.c linux-source-2.6.32.patched/drivers/char/agp/intel-agp.c --- linux-source-2.6.32.orig/drivers/char/agp/intel-agp.c 2010-04-16 10:09:32.000000000 +0200 +++ linux-source-2.6.32.patched/drivers/char/agp/intel-agp.c 2010-04-29 00:35:23.678619119 +0200 @@ -8,7 +8,10 @@ #include #include #include +#include #include "agp.h" +#include "intel-agp-add.h" +#include int intel_agp_enabled; EXPORT_SYMBOL(intel_agp_enabled); @@ -152,9 +155,9 @@ extern int agp_memory_reserved; static const struct aper_size_info_fixed intel_i810_sizes[] = { - {64, 16384, 4}, + {64, 16384 - I830_CC_DANCE_PAGES, 4}, /* The 32M mode still requires a 64k gatt */ - {32, 8192, 4} + {32, 8192 - I830_CC_DANCE_PAGES, 4} }; #define AGP_DCACHE_MEMORY 1 @@ -182,11 +185,14 @@ static struct _intel_private { */ int gtt_entries; /* i830+ */ int gtt_total_size; - union { - void __iomem *i9xx_flush_page; - void *i8xx_flush_page; - }; - struct page *i8xx_page; + void __iomem *i9xx_flush_page; + void *i8xx_cpu_flush_page; + void *i8xx_cpu_check_page; + void *i8xx_cpu_canary_pages[I830_CC_CANARY_FLOCK_PAGES]; + void __iomem *i8xx_gtt_cc_pages; + unsigned int i8xx_cache_flush_num; + unsigned int i8xx_gtt_whack_pagenum; + struct page *i8xx_pages[I830_CC_DANCE_PAGES + 1]; struct resource ifp_resource; int resource_valid; } intel_private; @@ -321,13 +327,11 @@ static int intel_i810_fetch_size(void) return 0; } if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { - agp_bridge->previous_size = - agp_bridge->current_size = (void *) (values + 1); + agp_bridge->current_size = (void *) (values + 1); agp_bridge->aperture_size_idx = 1; return values[1].size; } else { - agp_bridge->previous_size = - agp_bridge->current_size = (void *) (values); + agp_bridge->current_size = (void *) (values); agp_bridge->aperture_size_idx = 0; return values[0].size; } @@ -384,11 +388,6 @@ static void intel_i810_cleanup(void) iounmap(intel_private.registers); } -static void intel_i810_tlbflush(struct agp_memory *mem) -{ - return; -} - static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) { return; @@ -490,7 +489,6 @@ static int intel_i810_insert_entries(str goto out_err; } - agp_bridge->driver->tlb_flush(mem); out: ret = 0; out_err: @@ -511,7 +509,6 @@ static int intel_i810_remove_entries(str } readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); - agp_bridge->driver->tlb_flush(mem); return 0; } @@ -606,11 +603,11 @@ static unsigned long intel_i810_mask_mem static struct aper_size_info_fixed intel_i830_sizes[] = { - {128, 32768, 5}, + {128, 32768 - I830_CC_DANCE_PAGES, 5}, /* The 64M mode still requires a 128k gatt */ - {64, 16384, 5}, - {256, 65536, 6}, - {512, 131072, 7}, + {64, 16384 - I830_CC_DANCE_PAGES, 5}, + {256, 65536 - I830_CC_DANCE_PAGES, 6}, + {512, 131072 - I830_CC_DANCE_PAGES, 7}, }; static void intel_i830_init_gtt_entries(void) @@ -795,35 +792,220 @@ static void intel_i830_init_gtt_entries( static void intel_i830_fini_flush(void) { - kunmap(intel_private.i8xx_page); - intel_private.i8xx_flush_page = NULL; - unmap_page_from_agp(intel_private.i8xx_page); + int i; + + kunmap(intel_private.i8xx_pages[0]); + intel_private.i8xx_cpu_flush_page = NULL; + kunmap(intel_private.i8xx_pages[1]); + intel_private.i8xx_cpu_check_page = NULL; + + if (intel_private.i8xx_gtt_cc_pages) + iounmap(intel_private.i8xx_gtt_cc_pages); + + for (i = 0; i < I830_CC_CANARY_FLOCK_PAGES; i++) { + kunmap(intel_private.i8xx_cpu_canary_pages[i]); + intel_private.i8xx_cpu_canary_pages[i] = NULL; + } + + for (i = 0; i < I830_CC_DANCE_PAGES + 1; i++) { + __free_page(intel_private.i8xx_pages[i]); + intel_private.i8xx_pages[i] = NULL; + } - __free_page(intel_private.i8xx_page); - intel_private.i8xx_page = NULL; } static void intel_i830_setup_flush(void) { + int num_entries = A_SIZE_FIX(agp_bridge->current_size)->num_entries; + int i; + /* return if we've already set the flush mechanism up */ - if (intel_private.i8xx_page) - return; + if (intel_private.i8xx_pages[0]) + goto setup; - intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); - if (!intel_private.i8xx_page) + for (i = 0; i < I830_CC_DANCE_PAGES + 1; i++) { + intel_private.i8xx_pages[i] + = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); + if (!intel_private.i8xx_pages[i]) { + intel_i830_fini_flush(); + return; + } + } + + intel_private.i8xx_cpu_check_page = kmap(intel_private.i8xx_pages[1]); + if (!intel_private.i8xx_cpu_check_page) { + WARN_ON(1); + intel_i830_fini_flush(); return; + } - intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); - if (!intel_private.i8xx_flush_page) + intel_private.i8xx_cpu_flush_page = kmap(intel_private.i8xx_pages[0]); + if (!intel_private.i8xx_cpu_flush_page) { + WARN_ON(1); intel_i830_fini_flush(); + return; + } + + for (i = 0; i < I830_CC_CANARY_FLOCK_PAGES; i++) { + intel_private.i8xx_cpu_canary_pages[i] + = kmap(intel_private.i8xx_pages[i+2]); + if (!intel_private.i8xx_cpu_flush_page) { + WARN_ON(1); + intel_i830_fini_flush(); + return; + } + } + + /* Map the flushing pages into the gtt as the last entries. The last + * page can't be used by the gpu, anyway (prefetch might walk over the + * end of the last page). */ + intel_private.i8xx_gtt_cc_pages + = ioremap_wc(agp_bridge->gart_bus_addr + + num_entries*4096, + I830_CC_DANCE_PAGES*4096); + + if (!intel_private.i8xx_gtt_cc_pages) + dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); + +setup: + /* Don't map the first page, we only write via its physical address + * into it. */ + for (i = 0; i < I830_CC_DANCE_PAGES; i++) { + writel(agp_bridge->driver->mask_memory(agp_bridge, + page_to_phys(intel_private.i8xx_pages[i+1]), 0), + intel_private.registers+I810_PTE_BASE+((num_entries+i)*4)); + } + + intel_private.i8xx_cache_flush_num = 0; + intel_private.i8xx_gtt_whack_pagenum = 0; +} + +static void intel_whack_gtt_harder(void) +{ + void __iomem *whack_page = intel_private.i8xx_gtt_cc_pages + + (1 + I830_CC_CANARY_FLOCK_PAGES)*4096; + + whack_page += (intel_private.i8xx_gtt_whack_pagenum + % I830_CC_GTT_WHACK_PAGES)*4096; + + memset_io(whack_page, intel_private.i8xx_gtt_whack_pagenum, 4096); + + intel_private.i8xx_gtt_whack_pagenum++; +} + +static void intel_flush_mch_write_buffer(void) +{ + memset(intel_private.i8xx_cpu_flush_page, 0, + I830_MCH_WRITE_BUFFER_SIZE); + + mb(); + if (cpu_has_clflush) { + clflush_cache_range(intel_private.i8xx_cpu_flush_page, + I830_MCH_WRITE_BUFFER_SIZE); + } else if (wbinvd_on_all_cpus() != 0) + printk(KERN_ERR "Timed out waiting for cache flush.\n"); + mb(); +} + +static void intel_write_canary_flocks(void) +{ + int i, j; + + for (i = 0; i < 4096*I830_CC_CANARY_FLOCK_GTT_PAGES; i += sizeof(int)) { + unsigned int __iomem *write_pos_gtt + = intel_private.i8xx_gtt_cc_pages + 4096 + i; + writel(intel_private.i8xx_cache_flush_num, write_pos_gtt); + } + + for (i = 0; i < I830_CC_CANARY_FLOCK_CPU_PAGES; i++) { + for (j = 0; j < 4096; j += sizeof(int)) { + unsigned int *write_pos_cpu + = intel_private.i8xx_cpu_canary_pages[I830_CC_CANARY_FLOCK_GTT_PAGES + i] + + j; + *write_pos_cpu = intel_private.i8xx_cache_flush_num; + } + mb(); + if (cpu_has_clflush) { + clflush_cache_range(intel_private.i8xx_cpu_canary_pages[I830_CC_CANARY_FLOCK_GTT_PAGES + i], + 4096); + } else if (wbinvd_on_all_cpus() != 0) + printk(KERN_ERR "Timed out waiting for cache flush.\n"); + mb(); + } } -static void -do_wbinvd(void *null) +#define I830_GTT_MAX_RETRIES 100 +static void intel_wait_for_canary_flocks(void) { - wbinvd(); + int firstfail_gtt, firstfail_cpu; + unsigned int canary_cpu_read, canary_gtt_read; + int i, j, retries = 0; + + firstfail_cpu = firstfail_gtt = 0; + + for (i = 0; i < I830_CC_CANARY_FLOCK_GTT_PAGES; i++) { + mb(); + if (cpu_has_clflush) { + clflush_cache_range(intel_private.i8xx_cpu_canary_pages[i], + 4096); + } else if (wbinvd_on_all_cpus() != 0) + printk(KERN_ERR "Timed out waiting for cache flush.\n"); + mb(); + + for (j = 0; j < 4096; j += sizeof(int)) { + while (retries < I830_GTT_MAX_RETRIES) { + unsigned int *check_pos + = intel_private.i8xx_cpu_canary_pages[i] + j; + canary_cpu_read = *check_pos; + + if (canary_cpu_read + == intel_private.i8xx_cache_flush_num) + break; + + mb(); + if (cpu_has_clflush) + clflush(check_pos); + else + wbinvd_on_all_cpus(); + mb(); + + retries++; + intel_whack_gtt_harder(); + } + + if (retries == I830_GTT_MAX_RETRIES && !firstfail_cpu) + firstfail_cpu = i*4096 + j + 1; + } + } + + for (i = 0; i < 4096*I830_CC_CANARY_FLOCK_CPU_PAGES; i += sizeof(int)) { + while (retries < I830_GTT_MAX_RETRIES) { + unsigned int __iomem *check_pos + = intel_private.i8xx_gtt_cc_pages + + (1+I830_CC_CANARY_FLOCK_GTT_PAGES)*4096 + i; + + canary_gtt_read = readl(check_pos); + + if (canary_gtt_read == intel_private.i8xx_cache_flush_num) + break; + + retries++; + intel_whack_gtt_harder(); + } + + if (retries == I830_GTT_MAX_RETRIES && !firstfail_gtt) + firstfail_gtt = i+1; + } + + WARN_ONCE(retries == I830_GTT_MAX_RETRIES, "chipset flush timed out," + "gtt_read: %u, cpu_read: %u, " + "expected: %u, gtt_pos :%i, cpu_pos: %i\n", + canary_gtt_read, canary_cpu_read, + intel_private.i8xx_cache_flush_num, firstfail_gtt, + firstfail_cpu); } + /* The chipset_flush interface needs to get data that has already been * flushed out of the CPU all the way out to main memory, because the GPU * doesn't snoop those buffers. @@ -834,18 +1016,54 @@ do_wbinvd(void *null) * that buffer out, we just fill 1KB and clflush it out, on the assumption * that it'll push whatever was in there out. It appears to work. */ -static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) -{ - unsigned int *pg = intel_private.i8xx_flush_page; - memset(pg, 0, 1024); +/* Complaining once a minute about cache incoherency is enough! */ +DEFINE_RATELIMIT_STATE(i8xx_chipset_flush_ratelimit_cpu, 60*HZ, 1); +DEFINE_RATELIMIT_STATE(i8xx_chipset_flush_ratelimit_gtt, 60*HZ, 1); +static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) +{ + unsigned int offset1 + = (intel_private.i8xx_cache_flush_num * sizeof(int)) % 4096; + unsigned int offset2 + = (intel_private.i8xx_cache_flush_num * sizeof(int) + + 2048) % 4096; + unsigned int *p_cpu_read = intel_private.i8xx_cpu_check_page + offset1; + unsigned int *p_cpu_write = intel_private.i8xx_cpu_check_page + offset2; + unsigned int gtt_read, cpu_read; + + /* write check values */ + *p_cpu_write = intel_private.i8xx_cache_flush_num; + mb(); if (cpu_has_clflush) { - clflush_cache_range(pg, 1024); - } else { - if (on_each_cpu(do_wbinvd, NULL, 1) != 0) - printk(KERN_ERR "Timed out waiting for cache flush.\n"); - } + clflush(p_cpu_write); + clflush(p_cpu_read); + } else + wbinvd_on_all_cpus(); + writel(intel_private.i8xx_cache_flush_num, + intel_private.i8xx_gtt_cc_pages + offset1); + mb(); + + /* start chipset flush */ + intel_write_canary_flocks(); + intel_flush_mch_write_buffer(); + intel_wait_for_canary_flocks(); + + /* read check values */ + mb(); + gtt_read = readl(intel_private.i8xx_gtt_cc_pages + offset2); + cpu_read = *p_cpu_read; + + WARN(cpu_read != intel_private.i8xx_cache_flush_num + && __ratelimit(&i8xx_chipset_flush_ratelimit_cpu), + "i8xx chipset flush failed, expected: %u, cpu_read: %u\n", + intel_private.i8xx_cache_flush_num, cpu_read); + WARN(gtt_read != intel_private.i8xx_cache_flush_num + && __ratelimit(&i8xx_chipset_flush_ratelimit_gtt), + "i8xx chipset flush failed, expected: %u, gtt_read: %u\n", + intel_private.i8xx_cache_flush_num, gtt_read); + + intel_private.i8xx_cache_flush_num++; } /* The intel i830 automatically initializes the agp aperture during POST. @@ -901,7 +1119,7 @@ static int intel_i830_fetch_size(void) if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { /* 855GM/852GM/865G has 128MB aperture size */ - agp_bridge->previous_size = agp_bridge->current_size = (void *) values; + agp_bridge->current_size = (void *) values; agp_bridge->aperture_size_idx = 0; return values[0].size; } @@ -909,11 +1127,11 @@ static int intel_i830_fetch_size(void) pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { - agp_bridge->previous_size = agp_bridge->current_size = (void *) values; + agp_bridge->current_size = (void *) values; agp_bridge->aperture_size_idx = 0; return values[0].size; } else { - agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); + agp_bridge->current_size = (void *) (values + 1); agp_bridge->aperture_size_idx = 1; return values[1].size; } @@ -950,6 +1168,7 @@ static int intel_i830_configure(void) global_cache_flush(); intel_i830_setup_flush(); + return 0; } @@ -1007,7 +1226,6 @@ static int intel_i830_insert_entries(str intel_private.registers+I810_PTE_BASE+(j*4)); } readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); - agp_bridge->driver->tlb_flush(mem); out: ret = 0; @@ -1035,7 +1253,6 @@ static int intel_i830_remove_entries(str } readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); - agp_bridge->driver->tlb_flush(mem); return 0; } @@ -1232,7 +1449,6 @@ static int intel_i915_insert_entries(str global_cache_flush(); intel_agp_insert_sg_entries(mem, pg_start, mask_type); - agp_bridge->driver->tlb_flush(mem); out: ret = 0; @@ -1260,7 +1476,6 @@ static int intel_i915_remove_entries(str readl(intel_private.gtt+i-1); - agp_bridge->driver->tlb_flush(mem); return 0; } @@ -1279,7 +1494,6 @@ static int intel_i9xx_fetch_size(void) for (i = 0; i < num_sizes; i++) { if (aper_size == intel_i830_sizes[i].size) { agp_bridge->current_size = intel_i830_sizes + i; - agp_bridge->previous_size = agp_bridge->current_size; return aper_size; } } @@ -1901,7 +2115,6 @@ static const struct agp_bridge_driver in .configure = intel_i810_configure, .fetch_size = intel_i810_fetch_size, .cleanup = intel_i810_cleanup, - .tlb_flush = intel_i810_tlbflush, .mask_memory = intel_i810_mask_memory, .masks = intel_i810_masks, .agp_enable = intel_i810_agp_enable, @@ -1954,7 +2167,6 @@ static const struct agp_bridge_driver in .configure = intel_i830_configure, .fetch_size = intel_i830_fetch_size, .cleanup = intel_i830_cleanup, - .tlb_flush = intel_i810_tlbflush, .mask_memory = intel_i810_mask_memory, .masks = intel_i810_masks, .agp_enable = intel_i810_agp_enable, @@ -2139,7 +2351,6 @@ static const struct agp_bridge_driver in .configure = intel_i915_configure, .fetch_size = intel_i9xx_fetch_size, .cleanup = intel_i915_cleanup, - .tlb_flush = intel_i810_tlbflush, .mask_memory = intel_i810_mask_memory, .masks = intel_i810_masks, .agp_enable = intel_i810_agp_enable, @@ -2173,7 +2384,6 @@ static const struct agp_bridge_driver in .configure = intel_i915_configure, .fetch_size = intel_i9xx_fetch_size, .cleanup = intel_i915_cleanup, - .tlb_flush = intel_i810_tlbflush, .mask_memory = intel_i965_mask_memory, .masks = intel_i810_masks, .agp_enable = intel_i810_agp_enable, @@ -2233,7 +2443,6 @@ static const struct agp_bridge_driver in .configure = intel_i915_configure, .fetch_size = intel_i9xx_fetch_size, .cleanup = intel_i915_cleanup, - .tlb_flush = intel_i810_tlbflush, .mask_memory = intel_i965_mask_memory, .masks = intel_i810_masks, .agp_enable = intel_i810_agp_enable, @@ -2282,99 +2491,133 @@ static int find_gmch(u16 device) static const struct intel_driver_description { unsigned int chip_id; unsigned int gmch_chip_id; - unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ char *name; const struct agp_bridge_driver *driver; const struct agp_bridge_driver *gmch_driver; } intel_agp_chipsets[] = { - { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", + { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810", NULL, &intel_810_driver }, - { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", + { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810", NULL, &intel_810_driver }, - { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", + { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810", NULL, &intel_810_driver }, - { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", + { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_815_driver, &intel_810_driver }, - { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", + { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M", &intel_830mp_driver, &intel_830_driver }, - { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", + { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M", &intel_845_driver, &intel_830_driver }, - { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", + { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, "854", &intel_845_driver, &intel_830_driver }, - { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", + { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", &intel_845_driver, &intel_830_driver }, - { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, - { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", + { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL }, + { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865", &intel_845_driver, &intel_830_driver }, - { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, - { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", + { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL }, + { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", NULL, &intel_915_driver }, - { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", + { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G", NULL, &intel_915_driver }, - { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", + { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", NULL, &intel_915_driver }, - { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", + { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G", NULL, &intel_915_driver }, - { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", + { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", NULL, &intel_915_driver }, - { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", + { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", NULL, &intel_915_driver }, - { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", + { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", + { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, "G35", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", + { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", + { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", + { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", + { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, - { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, - { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", + { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL }, + { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL }, + { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, "G33", NULL, &intel_g33_driver }, - { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", + { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", NULL, &intel_g33_driver }, - { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", + { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", NULL, &intel_g33_driver }, - { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD", + { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, "IGD", NULL, &intel_g33_driver }, - { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD", + { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, "IGD", NULL, &intel_g33_driver }, - { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, + { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, "Mobile Intel® GM45 Express", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, + { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, + { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, + { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0, + { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, "B43", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, + { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, "G41", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, + { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, "IGDNG/D", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, + { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, "IGDNG/M", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, + { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, "IGDNG/MA", NULL, &intel_i965_driver }, - { PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, + { PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, "IGDNG/MC2", NULL, &intel_i965_driver }, - { 0, 0, 0, NULL, NULL, NULL } + { 0, 0, NULL, NULL, NULL } }; +static int __devinit intel_gmch_probe(struct pci_dev *pdev, + struct agp_bridge_data *bridge) +{ + int i; + bridge->driver = NULL; + + for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { + if ((intel_agp_chipsets[i].gmch_chip_id != 0) && + find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { + bridge->driver = + intel_agp_chipsets[i].gmch_driver; + break; + } + } + + if (!bridge->driver) + return 0; + + bridge->dev_private_data = &intel_private; + bridge->dev = pdev; + + dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); + + if (bridge->driver->mask_memory == intel_i965_mask_memory) { + if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) + dev_err(&intel_private.pcidev->dev, + "set gfx device dma mask 36bit failed!\n"); + else + pci_set_consistent_dma_mask(intel_private.pcidev, + DMA_BIT_MASK(36)); + } + + return 1; +} + static int __devinit agp_intel_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -2389,22 +2632,18 @@ static int __devinit agp_intel_probe(str if (!bridge) return -ENOMEM; + bridge->capndx = cap_ptr; + + if (intel_gmch_probe(pdev, bridge)) + goto found_gmch; + for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { /* In case that multiple models of gfx chip may stand on same host bridge type, this can be sure we detect the right IGD. */ if (pdev->device == intel_agp_chipsets[i].chip_id) { - if ((intel_agp_chipsets[i].gmch_chip_id != 0) && - find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { - bridge->driver = - intel_agp_chipsets[i].gmch_driver; - break; - } else if (intel_agp_chipsets[i].multi_gmch_chip) { - continue; - } else { - bridge->driver = intel_agp_chipsets[i].driver; - break; - } + bridge->driver = intel_agp_chipsets[i].driver; + break; } } @@ -2416,18 +2655,9 @@ static int __devinit agp_intel_probe(str return -ENODEV; } - if (bridge->driver == NULL) { - /* bridge has no AGP and no IGD detected */ - if (cap_ptr) - dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", - intel_agp_chipsets[i].gmch_chip_id); - agp_put_bridge(bridge); - return -ENODEV; - } bridge->dev = pdev; - bridge->capndx = cap_ptr; - bridge->dev_private_data = &intel_private; + bridge->dev_private_data = NULL; dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); @@ -2463,11 +2693,7 @@ static int __devinit agp_intel_probe(str &bridge->mode); } - if (bridge->driver->mask_memory == intel_i965_mask_memory) - if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) - dev_err(&intel_private.pcidev->dev, - "set gfx device dma mask 36bit failed!\n"); - +found_gmch: pci_set_drvdata(pdev, bridge); err = agp_add_bridge(bridge); if (!err) @@ -2493,22 +2719,7 @@ static int agp_intel_resume(struct pci_d struct agp_bridge_data *bridge = pci_get_drvdata(pdev); int ret_val; - if (bridge->driver == &intel_generic_driver) - intel_configure(); - else if (bridge->driver == &intel_850_driver) - intel_850_configure(); - else if (bridge->driver == &intel_845_driver) - intel_845_configure(); - else if (bridge->driver == &intel_830mp_driver) - intel_830mp_configure(); - else if (bridge->driver == &intel_915_driver) - intel_i915_configure(); - else if (bridge->driver == &intel_830_driver) - intel_i830_configure(); - else if (bridge->driver == &intel_810_driver) - intel_i810_configure(); - else if (bridge->driver == &intel_i965_driver) - intel_i915_configure(); + bridge->driver->configure(); ret_val = agp_rebind_memory(); if (ret_val != 0) diff -uprN -X linux-source-2.6.32.orig/Documentation/dontdiff linux-source-2.6.32.orig/drivers/gpu/drm/i915/i915_dma.c linux-source-2.6.32.patched/drivers/gpu/drm/i915/i915_dma.c --- linux-source-2.6.32.orig/drivers/gpu/drm/i915/i915_dma.c 2010-04-16 10:09:32.000000000 +0200 +++ linux-source-2.6.32.patched/drivers/gpu/drm/i915/i915_dma.c 2010-04-29 00:38:31.700619457 +0200 @@ -35,6 +35,7 @@ #include "i915_drv.h" #include "i915_trace.h" #include +#include /* Really want an OS-independent resettable timer. Would like to have * this loop run for (eg) 3 sec, but have the timer reset every time @@ -1227,7 +1228,7 @@ static int i915_load_modeset_init(struct * at the last page of the aperture. One page should be enough to * keep any prefetching inside of the aperture. */ - i915_gem_do_init(dev, prealloc_size, agp_size - 4096); + i915_gem_do_init(dev, prealloc_size, agp_size - I830_CC_DANCE_PAGES*4096); mutex_lock(&dev->struct_mutex); ret = i915_gem_init_ringbuffer(dev); diff -uprN -X linux-source-2.6.32.orig/Documentation/dontdiff linux-source-2.6.32.orig/drivers/gpu/drm/i915/i915_gem.c linux-source-2.6.32.patched/drivers/gpu/drm/i915/i915_gem.c --- linux-source-2.6.32.orig/drivers/gpu/drm/i915/i915_gem.c 2010-04-16 10:09:32.000000000 +0200 +++ linux-source-2.6.32.patched/drivers/gpu/drm/i915/i915_gem.c 2010-04-29 00:39:36.794619184 +0200 @@ -5052,7 +5052,9 @@ i915_gem_phys_pwrite(struct drm_device * if (ret) return -EFAULT; + mutex_lock(&dev->struct_mutex); drm_agp_chipset_flush(dev); + mutex_unlock(&dev->struct_mutex); return 0; } diff -uprN -X linux-source-2.6.32.orig/Documentation/dontdiff linux-source-2.6.32.orig/include/drm/intel-gtt.h linux-source-2.6.32.patched/include/drm/intel-gtt.h --- linux-source-2.6.32.orig/include/drm/intel-gtt.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-source-2.6.32.patched/include/drm/intel-gtt.h 2010-04-29 00:35:59.312620276 +0200 @@ -0,0 +1,13 @@ +/* Header file to share declarations between the intel-agp module and the i915 + * drm module + */ + +/* This denotes how many pages intel-gtt steals at the end of the gart. */ +#define I830_CC_CANARY_FLOCK_CPU_PAGES 2 +#define I830_CC_CANARY_FLOCK_GTT_PAGES 8 +#define I830_CC_GTT_WHACK_PAGES 16 +#define I830_CC_CANARY_FLOCK_PAGES (I830_CC_CANARY_FLOCK_CPU_PAGES +\ + I830_CC_CANARY_FLOCK_GTT_PAGES) +#define I830_CC_DANCE_PAGES (1 + I830_CC_CANARY_FLOCK_PAGES \ + + I830_CC_GTT_WHACK_PAGES) +#define I830_MCH_WRITE_BUFFER_SIZE 1024